1. Field of the Invention
The present invention relates to an image processing apparatus for performing so-called xcex1-blending and dithering and a method for the same.
2. Description of the Related Art
Computer graphics are often used in a variety of computer aided design (CAD) systems and amusement machines. Especially, along with the recent advances in image processing techniques, systems using three-dimensional computer graphics are becoming rapidly widespread.
In three-dimensional computer graphics, the color value of each pixel is calculated at the time of deciding the color of each corresponding pixel. Then, rendering is performed for writing the calculated value to an address of a display buffer (frame buffer) corresponding to the pixel.
One of the rendering methods is polygon rendering. In this method, a three-dimensional model is expressed as an composite of triangular unit graphics (polygons). By drawing the polygons as units, the colors of the pixels of the display screen are decided.
In polygon rendering, coordinates (x, y, z), color data (R, G, B, xcex1), homogeneous coordinates (s, t) of texture data indicating a composite image pattern, and a value of the homogeneous term q for the respective vertexes of the triangle in a physical coordinate system are input and processing is performed for interpolation of values inside the triangles.
Here, the homogeneous term q is, simply stated, like an expansion or reduction rate. Coordinates in a UV coordinate system of an actual texture buffer, namely, texture coordinate data (u, v), are comprised of the homogeneous coordinates (s, t) divided by the homogeneous term q to give xe2x80x9cs/qxe2x80x9d and xe2x80x9ct/qxe2x80x9d which in turn are multiplied by texture sizes USIZE and VSIZE, respectively.
FIG. 10 is a view of the system configuration of the basic concept of a three-dimensional computer graphics system.
In a three-dimensional computer graphics system, graphic drawing data and other data are given to a rendering circuit 5 having a rendering processor 5a and a frame buffer memory 5b from a main memory 2 of a main processor 1 or an I/O interface circuit 3 for receiving graphic data from the outside via a main bus 4.
In the rendering processor 5a, a frame buffer 5b for holding data to be displayed and a texture memory 6 for holding texture data to be applied on the surface of a graphic element to be drawn (for example, a triangle) are connected.
The rendering processor 5a performs processing for drawing a graphic element applied with texture on its surface for every graphic element.
The frame buffer 5b and the texture memory 6 are generally configured by a dynamic random access memory (DRAM).
In the system in FIG. 10, the frame buffer 5b and the texture memory 6 are configured to be physically separate memory systems.
When drawing image data, xcex1-blending is performed for blending (R, G, B) data included in the current image data and (R, G, B) data already stored in the frame buffer 5b by a blending value indicated by xcex1-data corresponding to the current image data. Furthermore, dithering is performed for thinning the image data after the xcex1-blending in consideration of the capacity of the frame buffer 5b etc., then the dithered (R, G, B) data is written back to the frame buffer 5.
In other words, xcex1-blending is processing for linear interpolation of two colors to apply a color between the two, while dithering is processing for adding noise data to the data subjected to the xcex1-blending and then thinning out the data to make a small number of colors appear as many colors.
FIG. 11 is a block diagram of an example of the configuration of an xcex1-blending circuit and a dithering circuit of the related art.
The xcex1-blending circuit 7 is composed of a multiplier 71 for multiplying current image data S (for example, an 8-bit integer expressing [0,255]) and a blending coefficient xcex1 (for example, an 8-bit integer expressing [0,2]), a subtractor 72 for subtracting the blending coefficient xcex1 from 1, a multiplier 73 for multiplying image data D already stored in the frame buffer memory 5b (for example, an 8-bit integer expressing [0,255]) and an output of the subtractor 72, an adder 74 for adding an output of the multiplier 71 and an output of the multiplier 73, and a clamp circuit 75 for extracting a valid value (for example, [0,255]) of a color value from the data obtained by the adder 74.
In the xcex1-blending circuit 7, as shown in FIG. 11, data xcex1xc3x97S+(1xe2x88x92xcex1)xc3x97D is obtained from input values S, D, and xcex1 in the same way as the output of the adder 74.
The dithering circuit 8 is configured by an adder 81 for adding error data E (for example, a 3-bit integer expressing [xe2x88x924,3]) as noise data to an output signal S7 of the xcex1-blending circuit 7, a clamp circuit 82 for extracting a valid value of a color value from an output of the adder 81, and a round-off circuit (dividing circuit) 83 for discarding (thinning out) the lower three bits of an output of the clamp circuit 82 and writing back the upper 5 bits to the frame buffer 5b. 
In the dithering circuit 8, as shown in FIG. 11, data xcex1(Sxe2x88x92D)+D+E is obtained from input values xcex1xc3x97S+(1xe2x88x92xcex1)xc3x97D and E in the same way as an output of the adder 81.
Summarizing the problems to be solved by the invention, as explained as above, however, since the xcex1-blending circuit 7 and the dithering circuit 8 are separately provided and configured to be connected in series in an image processing apparatus of the related art, the size of the circuit becomes large and the calculation time becomes long, which are obstacles to high speed processing.
Also, in a so-called built-in DRAM system of the related art in the above three-dimensional computer graphics system, there have been the following disadvantages when a frame buffer memory and a texture memory are provided separately in separate memory systems.
That is, there is the disadvantage that a frame buffer emptied due to a change of the display resolution cannot be used as a texture buffer or the disadvantage that the performance has to be sacrificed because of the large overhead, such as page exchange, of the DRAM in simultaneous access of the frame buffer memory and the texture buffer memory when the two are made physically integral.
An object of the present invention is to provide an image processing apparatus which can reduce the size of the circuits for xcex1-blending and dithering, can realize high speed processing, enables use of a memory region emptied due to a change in the display resolution for texture applications, can prevent an increase of overhead for page exchange etc., and enables flexible and high speed processing without causing a decline in performance, and a method for the same.
To attain the above object, according to a first aspect of the present invention, there is provided an image processing apparatus for performing xcex1-blending and dithering on image data, comprising a storage circuit in which at least display image data is drawn and a logic circuit for finding data on the amount of update of present image data to be drawn from image data already stored in the storage circuit using a given blending coefficient xcex1, finding the data comprised of noise data added to the image data stored in the storage circuit, adding the two obtained data to find data comprised of the noise data added to data obtained by linear interpolation of two colors, extracting valid value of color from the data, thinning out the extracted data, and writing back the same to the storage circuit.
According to a second aspect of the present invention, there is provided an image processing apparatus for performing rendering by receiving polygon rendering data including three-dimensional coordinates (x, y, z), R (red), G (green), and B (blue) data, a blending coefficient xcex1, homogeneous coordinates (s, t) of texture, and homogeneous tern q with respect to each vertex of the unit graphic, at least comprising a storage circuit for storing display image data and texture data required by at least one graphic element; a drawing data control circuit for finding data on the amount of update of present image data to be drawn from image data already stored in the storage circuit using a given blending coefficient xcex1, finding the data comprised of noise data added to the image data stored in the storage circuit, adding the two obtained data to find data comprised of the noise data added to data obtained by linear interpolation of two colors, extracting valid value of color from the data, thinning out the extracted data, and writing back the same to the storage circuit; an interpolation data generation circuit for interpolating polygon rendering data of vertexes of the unit graphic and generating interpolation data of pixels positioned inside the unit graphic; and a texture processing circuit for dividing homogeneous coordinates (s, t) of texture included in the interpolation data by a homogeneous term q to generate xe2x80x9cs/qxe2x80x9d and xe2x80x9ct/qxe2x80x9d, using texture data corresponding to the xe2x80x9cs/qxe2x80x9d and xe2x80x9ct/qxe2x80x9d to read texture data from the storage circuit, and performing processing for applying the texture data to the surface of a graphic element of the display use image data; the storage circuit, the drawing data control circuit, the interpolation data generation circuit, and the texture processing circuit being accommodated in one semiconductor chip.
According to a third aspect of the present invention, there is provide an image processing method for drawing in a storage circuit by performing xcex1-blending and dithering on image data, including the steps of performing in parallel processing for finding data on the amount of update of present image data to be drawn from image data already stored in the storage circuit using a given blending coefficient xcex1 and processing for adding noise data to the image data stored in the storage circuit and adding the data obtained by the two processing to find data comprised of the noise data added to data obtained by linear interpolation of two colors and extracting valid value of color from the data, thinning out the extracted data, and writing back the same to the storage circuit.
According to the present invention, data of an amount of update of current image data to be drawn from now with respect to image data already stored in the storage circuit is first obtained in a logic circuit by using a given blending coefficient xcex1. In parallel with this, data comprised of noise data added to the image data stored in the storage circuit is obtained.
Next, the data obtained by the two processings are added and data comprised of the noise data added to the image data after the xcex1-blending is obtained.
Then, valid value of colors is extracted from the added data and the extracted data is thinned out by rounding off processing etc. and written back to the storage circuit.
Namely, the xcex1-blending and the dithering are performed by a simplified circuit in a short time.
Also, according to the present invention, by mounting a DRAM or other storage circuit and a logic circuit together on a single semiconductor chip and by storing display image data and texture data required by at least one graphic element in the built in storage circuit, the built-in memory can be effectively used.
Furthermore, by giving identical functions as in the storage circuit to a plurality of modules in parallel, the efficiency of the parallel operation is improved. The usage efficiency of data declines and the performance can be improved only in limited conditions when only the number of bits in the data is large, however, by providing a plurality of modules having a certain extent of a function to improve to the average performance, bit lines can be efficiently used.
Also, the bit lines can be further efficiently used by improving the arrangement of the built-in storage circuit, that is, the address spaces occupied by the independent memory+function modules.
When frequently accessing a relatively fixed display region as in graphic drawing, by arranging display elements of adjacent addresses in mutually different memory blocks, the probability that the respective modules can be simultaneously operated increases and the drawing performance can be improved. The frequent accesses to a fixed region is caused when drawing an inside of a closed region of, for example, a triangle, in which the internal display elements are mutually adjacent. Therefore such accesses to a region have adjacent addresses.